The invention relates to a measurement amplification device for detecting a monopolar input signal and for generating a digital output value as a measure for the input signal, which comprises a switchable inverter which is controlled by a clock pulse generator with a polarity-reversal clock pulse, the inverter converting the input signal into a bipolar intermediate signal with the polarity-reversal clock pulse, and an A/D converter which generates the digital output signal depending on the intermediate signal.
The invention also relates to a measurement amplification method for detecting a monopolar input signal and for generating a digital output value as a measure of the input signal, wherein the input signal is converted, by means of a switchable inverter which is controlled by a clock pulse generator with a polarity-reversal clock pulse into a bipolar intermediate signal with the polarity-reversal clock pulse, and the digital output signal is generated by means of an A/D converter depending on the intermediate signal.
DE 694 24 931 T1 discloses a device and a method of this type. Methods and devices of this type for digitizing detection of measurement signals are known in the field of chopper amplification and chopper conversion and these are described in greater detail below.
Before the introduction of the chopper principle, a DC signal to be measured (referenced herein, in general, as “input signal”), the actual origin of which is irrelevant to the present invention, was pre-amplified with a DC amplifier and then digitized in an A/D converter. An integrating A/D converter, for example, is suitable for the digitizing.
The principle of the integrating A/D converter has long been known in many variants, for example, from DE 21 14 141, DE 28 20 601 C2 and DE 100 40 373 A1. In an integrating A/D converter, the measured signal is applied to an input of an operational amplifier configured as an integrator. For configuring as an integrator, the output of the operational amplifier is linked via a capacitor to its measured signal input. Also linked to the measured signal input of the operational amplifier is the feed line for a DC reference signal. This reference signal is applied at a working level only at certain times. During the remainder of the time, it is applied at a quantitatively lower rest level or is completely disconnected from the input of the operational amplifier. During a first pulse portion of a measuring clock pulse, during which the working level of the reference signal is not applied, the capacitor is charged up by the measured signal amplified in the operational amplifier. If, after a predetermined time period, the working level of the reference signal is switched on, the capacitor discharges during a second clock pulse portion, so that the integrator output signal declines. The time point of a zero-crossing or, more generally, a threshold-crossing by the integrator output signal, is detected by means of a comparator connected downstream, which itself initiates, via control means, the disconnection of the working level of the reference signal from the integrator input, so that a new measuring clock pulse can begin with the charging of the capacitor. The duration of the second clock pulse portion, that is, the time span during which the working level of the reference signal is applied to the integrator is measured with suitable time measuring means, for example, a clocked counter. The measured duration, referred to herein as the measured interval, represents a measure for the charging of the capacitor taking place in the first clock pulse portion, and therefore for the level of the measured signal. In the case of time measurement by means of a clocked counter, the counter value can be used directly as a digital measure of the measured signal.
In the past, a precise pre-amplification of the DC input signal presented difficulties due to the associated offset voltages and their drift. This was partially corrected by the introduction of the chopper principle which also brings advantages with regard to the suppression of 1/f noise.
When the chopper principle is used, the input signal is “chopped,” i.e., it is transformed by means of an inverter into a bipolar intermediate signal. The intermediate signal is essentially a bipolar rectangular signal, the polarity of which changes with a polarity-reversal clock pulse. The polarity-reversal clock pulse is predetermined by a clock pulse generator, which is coupled via a suitable control signal to the inverter or is an integral component of the inverter itself. The bipolar intermediate signal can be pre-amplified with known AC amplifiers. The pre-amplified AC intermediate signal can then be converted back to a DC measured signal with in-phase rectification and subsequent low-pass filtration, wherein the rectifier is typically controlled by the same clock pulse generator in order to ensure synchronization of the inverting and subsequent rectifying processes. The subsequent digitizing of the resulting DC signal can then take place as described above by means of an integrating A/D converter.
As an alternative to in-phase rectification and subsequent low-pass filtration of the previously inverted signal, it is known to sample the bipolar inverter output signal directly and at high frequency, wherein the difference between the mean values of the sampled values detected in respective successive half-periods of the inverter output signal can be used as a measure of the signal to be determined. Compared with the previously described method of in-phase rectification and subsequent low-pass filtration, this method has the advantage of digital elimination of the offset and drift of the AC pre-amplification. However, it has the disadvantage of needing a very high frequency sampler, which has a limited resolution.
A sigma-delta ADC which is known from US 2005/0219105 A1, samples a monopolar input signal according to a specially provided clock pulse generator and transfers said signal in discrete intervals to a bipolar integrator operating as an analog low-pass filter. The polarity of the pre-sampled signal is switched over according to a fixed polarity-reversal clock pulse supplied by the clock pulse generator, in order to compensate for any mismatch in two parallel pre-sampling capacitors and any possible offset in the measured signal. The integrator output signal is converted in a downstream comparator, which operates as a 1-bit ADC, into a very high frequency digital pulse sequence which is fed to a reference signal switch operating as a 1-bit ADC. The reference signal switch changes the polarity of the reference signal that is also applied to the integrator according to the HIGH-level and/or LOW-level of the 1-bit signal, in order to achieve the negative feedback of the digital 1-bit signal with the input signal of the analog filter that is characteristic of sigma-delta conversion.
An ADC circuit is known from U.S. Pat. No. 5,229,772, wherein a monopolar input signal is likewise pre-sampled and transferred in discrete intervals together with the also pre-sampled reference signal to an integrator. In the context of the pre-sampling, in order to increase the charging level, the polarity of the measured signal and the reference signal, respectively, is switched over. However, only one polarity of the measured signal is applied, discontinuously, to the integrator. The polarity change in the measured signal and the reference signal is carried out using a separate clock pulse generator. The polarity of the reference signal is also reversed in order to create integration and de-integration phases in the manner described above, depending on the output signal of a comparator connected downstream of the integrator.
A device with voltage/frequency-conversion of a detuning signal of a measuring bridge is known from DE 36 33 790 A1, wherein according to the principle of alternating integration and de-integration of the detuning signal and comparison with a threshold value in a comparator, a pulse train which has a frequency that is representative of the bridge detuning is generated. In the known device, the polarity of the supply voltage of the measuring bridge is arbitrarily reversed according to an external polarity-reversal clock pulse. The detuning signal applied to the measuring bridge also changes its polarity accordingly, and this normally takes place during an integration phase, compared to the duration of which the duration of the de-integration phase is negligibly short. In order to avoid misplaced pulses occurring in the pulse train, a charge balance cycle which causes a delay of the pulse to be output is set in motion, and this also triggers the next de-integration phase.